In semiconductor wafer polishing, the advent of very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits has resulted in the packing of relatively more devices in smaller areas on a semiconductor substrate, which may necessitate greater degrees of planarity for the higher resolution lithographic processes that may be required to enable said dense packing. In addition, as copper and other relatively soft metals and/or alloys are increasingly being used as interconnects due to their relatively low resistance, the ability of the CMP pad to yield relatively high planarity of polish without significant scratching defects on the soft metal surface may become relatively critical for the production of advanced semiconductors. High planarity of polish may require a hard and rigid pad surface to reduce local compliance to the substrate surface being polish. However, a relatively hard and rigid pad surface may tend to also cause scratching defects on the same substrate surface thus reducing production yield of the substrate being polished.